The desireability of extremely small memory cells in DRAMs is widely known in the art. DRAM fabrication has reached the point where memory cells may no longer occupy a large surface area of the integrated circuit but must be vertically integrated. To this end trench capacitor and trench transistor cells have been developed (See e.g. U.S. App. Ser. No. 679,663 and Japanese Published Application No. 59-19366(A), both of which are hereby incorporated by reference). The quest to develop smaller vertically integrated DRAM cells is limited by, among others, two factors. First, most DRAM cells require isolation structures between the cells to avoid crosstalk of data between cells; this occupies substantial surface area of the integrated circuit. Second, allowance must be made for alignment tolerances. Thus, although a cell may ideally be laid out in a very small space, area must be reserved on the integrated circuit for misalignment of components formed on the surface or in the top of the integrated circuit.